Bug: Simulink Design Verifier blocks with output ports always output zero
| Submitted | Product | Status | ||
|---|---|---|---|---|
| 2019-03-26 | Reactis for Simulink | Resolved in 2018.2.2 (released May 16, 2019; release notes) Resolved in 2018.0.4 (released May 16, 2019; release notes) | ||
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If a model contains Simulink Design Verifier blocks ("Design Verifier Test Condition" or "Design Verifier Test Objective") which are set to show their output port then and in Reactis the "Ignore Design Verifier blocks" option is selected then the output of those blocks is always 0, even though the output should mirror the block's input. | ||||